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ADC0808 is a set of single-chip CMOS device data acquisition components


The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with 8-bit analog to analog range regulation voltage reference microprocessor compatible control logic. 8-bit conversion technology. The converter features a high 8-channel multiplexer and address logic impedance chopper-stabilized comparator, and the 256R asks for any single-ended analog signal. The unit does not require external zero and full adjustment of major specifications. Easily connected to the microprocessor provided by the latch ADC0809 provides high speed, high precision, minimizes temperature dependence, long-term excellent accuracy and repeatability, and consumes minimal power. These features make the device ideal for process and machine control to application consumer and automotive applications. For 16-channel multiplexers with common outputs.

 

feature:

 

Easily connect all microprocessors.

A proportional or 5 VDC or digitizer, 8-channel multiplexer.

No zero or full-scale adjustment A/D converters use successive approximation as a conversion technique with a high 8-channel multiplexer and address logic.

0V to VCC input range divider with analog switch tree and a

The output conforms to the TTL voltage level specification for successive approximation registers. 8 channels

The ADC0808 is equivalent to the MM74C949 multiplexer that provides direct access to any of the eight single-ended analog signals.

 

Main specifications:

 

 

ADC0809 is equivalent to MM74C949-1

Resolution: 8-bit decoded multiplexer address input and latched TTL

Total unadjustable error: ±1⁄2LSB and ±1 LSB TRI-STATE output.

Single power supply: 5 VDC ADC0808, ADC0809 design has been implemented

Low power consumption: Optimized by combining the best aspects 15 mW

 

Connection Diagram:

 

Connection Diagram

 

ADC0808-N package drawing:

 

ADC0808-N

 

ADC0809-N package drawing:

 

ADC0809-N

 

 

The heart of the single-chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to provide fast, accurate and repeatable conversion over a wide temperature range. The converter is divided into 3 main parts: 256R ladder network, successive approximation registers and

 

Comparison. The digital output of the converter is correct. Select the 256R ladder network method (below in Figure 1) instead of the monotonicity inherent in the traditional R / 2R ladder diagram to ensure that the digital code is not lost. Monotonicity is especially important in loop control systems when closed. A non-monotonic relationship can cause oscillations, which would be a catastrophic system. In addition, the 256R network does not cause a load change in the reference voltage. The bottom and top resistances of the ladder network in Figure 1 below differ from this value by the rest of the network. The difference in these resistors results in an output characteristic that is symmetric using the zero and full scale points of the transfer curve. The first output transition occurs when the analog signal has reached +1⁄2LSB, and the subsequent output transition occurs every 1 LSB until full scale. The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR converter, the n-bit converter requires n iterations. Figure 2 below shows a typical example converter of 3 bits. In ADC0808, ADC0809, the approximation technique is extended to an 8-bit network using 256R. The successive approximation register (SAR) of the A/D converter resets the start pulse on the rising edge of the start conversion. The conversion begins on the falling edge of the start transition pulse. The conversion in progress will be interrupted by receiving a new start transition pulse. The end of conversion (EOC) output can be connected to the SC input by implementing a continuous conversion. If used in this mode, it should be applied after the external start conversion pulse is powered up. After rising, the end of the conversion will go low between 0 and 8 clock pulses to begin the transition. The most important part of the A / D converter is the comparator. It is this part that is responsible for the final accuracy of the entire converter. It is also a comparator drift that affects the repeatability of the largest device. The chopper-stabilized comparator provides the most efficient method converter requirements to meet all requirements. A chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through the high gain AC amplifier and the DC level is restored. This technique limits the drift component of the amplifier because drift is a DC component that cannot pass through the AC amplifier. This makes the entire A/D converter very insensitive to temperature, long-term drift and input offset errors.

 

 

 

A good example of a ratio sensor is a potentiometer used as a position sensor. The position wiper is proportional to the output voltage and the output voltage is the ratio of the full-scale voltage across it. Since the data is expressed as a percentage of full scale, the reference requirements are greatly reduced, eliminating many of the errors and cost sources of many applications. One of the main advantages of the ADC0808 is that the ADC0809 has an input voltage range equal to the power supply range, so the sensors can be directly connected to the power supply and the power supply. Their outputs are directly connected to the multiplexer input. Proportional sensors, such as potentiometers, strain gauges, thermistor bridges, pressure sensors, etc., are suitable for measuring proportional relationships; however, many types of absolute standards must be referenced, such as voltage or current. This means that the system-dependent system reference full-scale voltage must be used to the standard voltage. For example, if VCC = VREF = 5.12V, then the full-scale range is divided into 256 standard steps. The minimum standard step size is 1 LSB, then 20 mV.

 

The resistor step limits the voltage from the ladder resistor to 8 times compared to the selected voltage during the conversion. These voltages are coupled to the comparator through an analog switch tree, and the analog switch tree is referenced to the power supply. The voltage must be at the top, center and bottom of the ladder to maintain normal operation. The top of the ladder, Ref(+), should not be more aggressive than the supply, the bottom of the ladder, Ref(-), should not be more negative than the ground. The center of the trapezoidal voltage must also be close to the center supply because the analog switch tree changes from an N-channel switch to a P-channel switch. These automatically meet the limits in the ratio system and can be easily met in a ground reference system. The figure below shows a ground reference system with separate power supplies and references. In this system, the supply must be trimmed to match the reference voltage. For example, if 5.12V is used, the same voltage within 0.1V should be adjusted.

 

The ADC0808 requires less than one milliamp of supply current, so developing power from the reference voltage is easy to accomplish. In Figure 1 below, a ground reference system is shown from which a power reference is generated. The buffer shown can be a sufficiently driven operational amplifier to provide the desired bus drive for the mA supply current, or if the capacitor bus is driven by the output, the large capacitor will provide the transient supply current as shown in Figure 2. LM301 It has been compensated to ensure a stable capacitance at 10μF output load. The top and bottom trapezoidal voltages must not exceed VCC and ground, respectively, but they can be symmetric below VCC and greater than ground. The center of the trapezoidal voltage should always be supplied close to the center. By using a, the sensitivity of the converter (ie, the size of the LSB step is reduced) can be increased by a symmetric reference frame. In Figure 3 below, the 2.5V reference voltage is symmetrically centered around VCC / 2, since the same current flows into the same resistor. The system has a 2.5V reference voltage that allows half of the LSB bit size to be a 5V reference system.

 

 

 

 

Analog comparator input:

 

The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitance. These are alternately connected to the output of the ladder resistor/switch tree network and part of the operation of the comparator input chopper-stabilized comparator. The average value of the comparator input current varies directly with the clock frequency and VIN as shown. If the analog input does not use a filter capacitor and the source impedance is low, the comparator input current should not introduce a converter error because the transient generated by the capacitor discharge will die before being output at the gate comparator output. If input filter capacitors are needed to reduce noise and signal conditioning, they tend to average out the dynamic comparator input current. It then predicts the characteristics of the DC bias current with its effect.