Home About us Agent Brand Our history Press Room Help Contact Us

8x oversampling digital interpolation of filter DF1706

The DF1706's system clock can be supplied via an external clock signal at XTI (Pin 6) or through an on-chip crystal oscillator. The system clock rate must be running at 128FS, 192fS, 256fS, 384fS, 512fS or 768fS, where fS is the audio sample rate. When a 128FS or 192fS system clock is applied to DF1706, the oversampling rate (OSR) digital filter of DF1706 should be 4x instead of 8x. The OSR can be selected in the software mode MODE 2 register or x4 bit by the hardware mode of the x4 pin (pin 21). However, it should be noted that the 768fS system clock cannot be used when fS is larger than 48kHz. Both the 128FS and 192fS system clocks can be used when fS is larger than 96kHz. In addition, the on-chip crystal oscillator is limited to the maximum frequency of Quincy 24.0MHz. Table I shows the sampling rate for a typical system clock frequency selection. The DF 1706 includes a system clock detection circuit that determines that the system clock rate is in use. The circuit compares the frequency with the system clock input (XTI) rate of the LRCIN input to determine the multiplication of the system clock. Ideally, LRCIN and BCKIN should be derived from the system clock to ensure proper synchronization. If the phase difference BE-twisted system clock and LRCIN are greater than ±4 bit clock (BCKIN), the system's synchronization and LRCIN clock will be automatically performed by DF1706. The timing requirements for the system clock input are shown in Figure 1.


figure 1:


The DF1706 has both an internal power-on reset circuit and a reset pin, RST (14-pin), to provide an external reset signal. An internal power-on reset is performed on automati- when power is applied to the DF1706, as shown in Figure 2. The RST pin can be used to synchronize the DF1706 with a system reset signal, as shown in Figure 3. During a power-on reset (1024 system clocks), the outputs of BCKO, DOL, and DOR are forced low, and the output of WCKO is forced high. For external forced reset, the output of BCKO, DOL and DOR is forced low and the high cycle (1024 system clocks) is forced during the initialization of the WCKO output, then a high transition of the RST pin occurs after the low (see image 3) .


figure 2:



figure 3:



PCB layout guide


In order to obtain the performance specified from the DF1706 and its associated D/A converter, proper printed circuit board layout is critical. Figure 4 shows two methods for achieving optimal audio performance. Figure 4(a) shows a standard, mixed-signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The land should be placed in a split plane that separates the routing and power planes. The 4DF1706 and all digital circuits should be placed in the digital section, while the audio D/A converter (S) and analog circuitry should be placed over the analog section board. Common connection reasons between numbers and simulations are required and are done at a single point, as shown.


For Figure 4(a), the digital signal should be routed from DF1706 to audio D/A using a short direct converter (S) connection to reduce the radiated high frequency amount of Quincy energy. Series resistors can be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present in these signals, if desired. The value of 50Ω to 100Ω is recommended as a starting point, but designers should try to get the best results with resistance values. Figure 4(b) shows an improved method, high-quality Mans, mixed-signal board layout. This method will digitally isolate the DF1706 and audio D/A converters (multiple) and provide a digital and analog part of the fully isolated board. The ISO150 dual digital coupler provides excellent isolation and operation speeds of up to 80Mbps.


Figure 4:



Power supply and bypass


The operation required by the DF1706 + 5V single power supply. The power supply should be bypassed by a 10μF, 0.1μF capacitor in parallel. This capacitor should be placed as close as possible to VDD (Pin 22). Aluminum electrolytic or tantalum capacitors can be used for values of 10 μF and can be used for ceramics of values of 0.1 μF.


Basic circuit connection


Figures 5 and 6 show the connection of the basic circuit DF1706. Fig. 5 shows the connection mode control for the device mode connection control and the software as shown in Fig. 6. Note that the C1 and C2 are placed in both figures because they are physically close to the DF1706.


Figure 5:



Figure 6: